1 x 120-minute lecture weekly
1 x 60-minute tutorial weekly
1 x 120-minute project work weekly
1 ENGR3701 - Computer Organisation and Design
2 Admission into GDPEE-Graduate Diploma in Engineering (Electronics)
2a Admission into HBSC-Bachelor of Science (Honours)
2b Admission into MEE-Master of Engineering (Electronics)
2c Admission into GDPEB-Graduate Diploma in Engineering (Biomedical)
2d Admission into HBIT-Bachelor of Information Technology (Honours)
2e Admission into BENGCH-Bachelor of Engineering (Computer Systems) (Honours)
2f Admission into MEB-Master of Engineering (Biomedical)
2g Admission into BENGCNSH-Bachelor of Engineering (Computer and Network Systems) (Honours)
Must Satisfy: ((1) or ((2 or 2a or 2b or 2c or 2d or 2e or 2f or 2g)))
Enrolment not permitted
ENGR4731 has been successfully completed
Assumed knowledge
ENGR2721 Microprocessors. Students undertaking the one year honours programs should check to make sure they have the appropriate background from their undergraduate degree/s.
Topic description
  1. Instruction-set design
  2. Instruction level-parallelism and Dynamic Scheduling
  3. Memory hierarchy; cache memory; virtual memory
  4. Bus management
  5. System peripherals
  6. Multiprocessor Architectures and Interconnect
  7. Thread-Level Parallelism
  8. DSP/GPU architectures
Educational aims

This topic aims to introduce students to the design of modern microprocessor based systems. The various component modules of a microprocessor system are studied with a view to understanding their interaction and implementation issues. Laboratory-based sessions are used to familiarise students with the use of Digital Signal Processor (DSP) and Graphical Processing Unit (GPU) architectures.

Expected learning outcomes
On completion of this topic you will be expected to be able to:

  1. Measure and objectively evaluate machine performance
  2. Identify and realise optimal implementation strategies to meet specific computing performance requirements
  3. Understand strategies for interfacing microprocessor system components
  4. Understand the architectural concepts and merits of DSP and GPU devices
  5. Demonstrate capability in developing optimized algorithms for real-time implementation on a DSP architecture
  6. Adapt to future trends in computer architecture design
  7. Commence further industry / academic training in research and development in the field of computer architecture and other related disciplines
  8. Work independently and also as a member of a project team

Key dates and timetable

(1), (2)

Each class is numbered in brackets.
Where more than one class is offered, students normally attend only one.

Classes are held weekly unless otherwise indicated.


If you are enrolled for this topic, but all classes for one of the activities (eg tutorials) are full,
contact your College Office for assistance. Full classes frequently occur near the start of semester.

Students may still enrol in topics with full classes as more places will be made available as needed.

If this padlock appears next to an activity name (eg Lecture), then class registration is closed for this activity.

Class registration normally closes at the end of week 2 of each semester.

Classes in a stream are grouped so that the same students attend all classes in that stream.
Registration in the stream will result in registration in all classes.
  Unless otherwise advised, classes are not held during semester breaks or on public holidays.