1 x 2-hour lecture weekly 1 x 1-hour tutorial weekly 1 x 2-hour workshop weekly 1 x 2-hour laboratory weekly
Enrolment not permitted
1 of ENGR3701, ENGR4751, ENGR8781 has been successfully completed
Knowledge such as acquired in ENGR1201 Electronics or ENGR8703 Electronics GE and knowledge such as acquired in ENGR2721 Microprocessors,
This topic covers: Hardware Description Languages - VHDL including: Behavioural Design, Structural Design, Synthesis, Simulation; Field Programmable Gate Arrays; Computer Organisation; Instruction Set Architectures; Datapath Design, Computer Arithmetic, Performance Metrics, Microprogramming; Pipeline Architecture, Memory Hierarchy, Bus Interconnect, Storage Devices.
This topic introduces students to the fundamental principles of computer organisation and design. The topic is structured to allow students to apply fundamental digital design concepts (taught in Digital Electronics 1) to the development of microprocessor devices and embedded systems. The topic's aim are realized through the use of computer aided design tools that enable students to design and implement microprocessor architectures on reconfigurable integrated circuits within the laboratory.
Expected learning outcomes
At the completion of the topic, students are expected to be able to:
Design microprocessor circuits
Design, simulate, and synthesise embedded systems using the VHDL programming language
Understand the use of CAD (computer aided design) tools for field programmable gate array (FPGA) design
Understand the concepts involved in designing instruction set architectures
Understand the concepts involved in quantifying and improving computer performance
Understand techniques used in interfacing memory and data storage systems
Identify appropriate design solutions for given requirements
Critically evaluate using appropriately sourced evidence the suitability of particular design strategies for achieving an optimal architecture
Use VHDL, be able to develop, implement and analyse a microprocessor design
Work independently and as a member of a project team
Key dates and timetable
Timetable details for 2019 are no longer published.
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